This invention relates generally to the planarization of integrated circuit surfaces. More particularly, it relates to the planarization of wide dielectric filled isolation trenches in the surface of a semiconductor substrate.
Trenches filled with dielectric insulating material with as silicon oxide for isolating devices in integrated semiconductor circuits are known to provide significant device density improvements over other isolation techniques. However, where a dielectric or other insulating material has been deposited in a trench, a highly irregular surface can result. If this irregularity is excessive, it can cause anomolous device leakage, reduced isolation integrity, and subsequent metallization defects. Because this effect may be magnified as the result of subsequent processing, it is important for the trenches and the substrate containing the devices isolated by the trenches to be as planar as possible.
Various types of trenches are known in the art. Deep narrow trenches are typically used to isolate one device from another in the integrated circuit. For examples, a trench may isolate one transistor from another. Shallow trenches are utilized to isolate individual elements within a device; e.g., to isolate the base from the collector in a bipolar transistor (source from drain in CMOS FET). Wide trenches are also commonly used in the art and can serve as areas where metallization patterns will be deposited. Shallow, deep, and wide trenches can be used interchangeably to isolate devices.
Typically, these trenches are filled with dielectric materials such as silicon dioxide or silicon nitride. These materials are commonly deposited by conformal coating processes such as chemical vapor deposition (CVD).
In a single integrated circuit, therefore, a variety of trenches can be present, all of which must be filled with dielectric material for isolation and planarized to prevent anomolous leakages or metallization defects. While a relatively narrow trench is relatively easy to planarize with a conformal isolation layer, it is much more difficult to fully planarize a wide trench. A process which will fully planarize a narrow trench will generally remove much of the dielectric from a wide trench.
Various methods have been proposed to planarize wide dielectrically filled trenches in the prior art. One method proposed is to form a wide organic plug, which can be converted to a dielectric, in the deep trench. The organic material, such as resin glass, deposited in the trench is then exposed to electron beam radiation to render it insoluble in a stripping solvent. The excess material is removed in a suitable solvent or etching solution. The plug of organic material is converted to an oxide by heating it in an oxygen ambient. A layer of silicon dioxide is then deposited over the entire substrate and etched back to planarize the surface. This method suffers from the impurities present in the organic material and the need for accurate registration of the electron beam to the trench. Also, an electron beam exposure tool is expensive and its use should be avoided whenever possible to reduce manufacturing costs.
Other methods of filling wide trenches have formed wide dielectric plug in the wide trench by masking a portion of the area above the wide trenches with photorisist. After a conformal coating of dielectric has been deposited over the substrate, a layer of photoresist is applied and patterned using standard photolithography techniques. The wide dielectric plug is formed in the middle of the wide trench by an etch step, essentially converting the wide trench into two narrow trenches at either side of the original wide trench. The narrow trenches are then filled with a second conformal coating of dielectric and photoresist and etch back to planarize the surface. This method requires the use of an expensive photolithography tool and the need to provide accurate registration of the photoresist mask to the trench structure below.
Yet other methods have sought to planarize wide trenches by assuring a layer of photoresist applied to the top of the conformal layer of dielectric is totally planar, and then etching the resist and silicon oxide nonselectively in a 1:1 etch rate ratio. These techniques begin by forming a plug of photoresist over the deep trench, either by standard photomasking techniques or by a self-aligned process, and then apply a second layer of photoresist to achieve a planar surface. These methods suffer from the non-uniform etch properties of resist and the fact that a 1:1 etch ratio is difficult to achieve and maintain in a manufacturing environment. Additionally, a resist layer can form ripples or waves during the planarizing resist reflow or during the reactive etch step itself. These effects combine to cause the dielectric in the wide isolation trench to have a rippled surface, which may not be planar with the surface of the semiconductor substrate if the 1:1 etch ratio is not maintained.